Electronic packages of the variety described above are known in the art. Examples are defined in detail in U.S. Pat. Nos. 5,435,732 (Angulas et al), 5,397,921 (Karnezos), 5,386,341 (Olson et al), 5,278,724 (Angulas et al), 4,873,123 (Canestaro et al), 4,000,842 (Burns), 4,005,472 (Harris et al) and 4,899,207 (Hallowell et al). Methods for forming electronic packages of the variety described above are defined in U.S. Pat. Nos. 5,029,386 (Cha et al), 5,336,564 (Moldavsky), 5,034,591 (Fang), 4,979,663 (Sofia et al), 5,098,008 (Visa et al), and IBM Technical Disclosure Bulletin Vol. 30, No. 4, pp. 1511-1512, September, 1987.
As defined therein, such packages may include a chip electrically coupled to one side of a flexible circuit member which is typically of a dielectric, e.g., polyimide, having at least one layer of circuitry, e.g., copper. Such a chip may be coupled, electrically, to the flexible circuit member's circuitry using solder. See, e.g., U.S. Pat. No. 5,435,732 at FIG. 10. A well-known technique for accomplishing such a solder coupling includes what is known in the industry as a controlled collapse chip connection ("C4") procedure. Another known process is a thermal compression bonding ("TCB") procedure. Because both processes are known, further description is not believed necessary. The flexible circuitry ("tape") may then be coupled electrically to respective circuitry, e.g., copper pads or lines, formed on the surfaces of another flex circuit, a more rigid printed circuit board, a ceramic substrate, or the like. Circuit boards, usually comprised of several layers of dielectric material, e.g., fiberglass-reinforced epoxy resin, interspersed with various conductor levels, e.g., power, signal and/or ground planes, and often including plated through holes and/or internal conductive vias are known in the art and further definition is not believed necessary.
Because of the disparate nature of chip manufacturing methods from circuitized substrate methods (such as methods of producing printed circuit boards of flexible tape substrates), it is necessary to prepare a chip and substrate independently and subsequently join these elements electrically. The art of forming such a connection in the face of significant manufacturing constraints encompasses problems such as dimensional tolerancing, material selection, bonding methods, and mechanical reliability of the resulting bonds. It is known that chip sizes continue to shrink, yet the number of signals (electrical connections each requiring a separate bond) continue to grow as the art of chip manufacturing advances. Therefore, a method of bonding many electrical signal paths in a small, dense area from the chip to a circuitized substrate is of great utility in the field of electronic packaging. A method which can be used to form mechanically strong connections is desired for robustness and reliability, and a method which allows for increased manufacturing yield is also of great interest for economic reasons.
It is believed that an electronic package assembly capable of overcoming the several aformentioned problems, and a method of making same, would consitute significant advancements in the art.
The invention as taught herein allows the use of an electrically conductive member as a medium for an interim circuit path between a chip and a circuitized substrate, with a simple means of forming the member into hundreds or thousands of separate, robust electrically conductive paths. The use of a member separate from either the chip or substrate allows for several significant advantages. First, the material chosen for the member can be a material which will optimally bond to both the chip and the substrate, with appropriate surface finish for each bond. Second, the separate member need not be subjected to any of the required processing steps of the chip and/or substrate, avoiding damage and yield loss. Finally, manufacturing methods specific to forming the delicate, precise shapes for the separate member are possible and these methods need not be applied to either the chip or substrate.
Another significant feature of the invention is the use of tear-off notches to remove retention members after bonding. Because these are removed after bonding, the retention members serve to dimensionally control the location of the numerous signal lines throughout the bonding process, assuring that the signal lines will be aligned with the desired bonding locations. Locating the retention members fairly close to the bonding locations of the signal lines maximizes their effect. Locating the notches outside the signal line region of interest (the conductive path between the chip and substrate) so that signal line electrical impedance is not altered is an important advantage of the invention. Further, the ability to use retention members which are of the same material as the signal lines is an advantage. The use of the same material assures simple dimensional control as temperature changes are applied (e.g., as during thermocompression bonding) and enables simple photoetching and plating manufacture using known methods. Still further, because the retention members are totally removed after bonding, there is no need to be concerned with the specific electrical (dielectric or not) or mechanical properties thereof; only the numerous signal lines between the chip and substrate which remain are of interest to the completed electronic package.